The present invention relates to a logic circuit and, more particularly, to a CMOS (complementary metal oxide semiconductor) logic circuit well adaptable for decoders, ROMs (read only memories) and the like comprised of P-channel MOS (metal oxide semiconductor) transistors and N-channel MOS transistors.
Basically, the CMOS logic circuit is so arranged that a plurality of MOS transistors of the same channel type are connected in parallel, a plurality of MOS transistors of the opposite channel to that of the parallel connected ones are connected in series, and a logic output signal is taken out from the connection point between the parallel connected MOS transistors and the serially connected MOS transistors.
Normally, the CMOS logic circuit is applied for decoders, ROMs and the like. In the specification, a case where it is applied to a decoder will be described for ease of explanation.
FIG. 1 shows a conventional decoder comprised of a CMOS logic arrangement. Table 1 shows a truth table illustrating a relation between binary code input signals and decimal code output signals, which is used in the decoder shown in FIG. 1.
TABLE 1 ______________________________________ (Truth Table) Binary Coded Inputs Decimal Coded Outputs D C B A 0 1 2 3 4 5 6 7 8 9 ______________________________________ L L L L H L L L L L L L L L L L L H L H L L L L L L L L L L H L L L H L L L L L L L L L H H L L L H L L L L L L L H L L L L L L H L L L L L L H L H L L L L L H L L L L L H H L L L L L L L H L L L L H H H L L L L L L L H L L H L L L L L L L L L L L H L H L L H L L L L L L L L L H ______________________________________
In FIG. 1 illustrating the decoder, there is illustrated a circuit construction for producing decimal coded output signals of `0`, `5` and `9` alone, for simplicity of illustration. The circuit construction for producing, for example, output signals `1` to `4`, `6` to `8`, `10` are omitted in the figure. In FIG. 1, N1 to N12 designate N-channel MOS transistors and P1 to P12 P channel MOS transistors, respectively. The N channel MOS transistors N1 to N4 enclosed by dotted line are connected in parallel. Similarly, a group of transistors N5 to N8 enclosed by dotted line 14 and another group of transistors N9 to N12 enclosed by dotted line 16 are each connected in parallel, respectively.
A group of P channel MOS transistors P1 to P4 within a dotted line block 18, a group of P channel MOS transistors P5 to P8, within a dotted line block 20 and a group of P channel MOS transistors P9 to P12 within a dotted line block 22 are each connected in series, as shown.
A terminal 24, normally connected to a zero potential point, is a power source terminal for the N channel MOS transistors N1 to N12. A terminal 26, normally connected to +5 V, is a power source terminal for the P channel transistors P1 to P12. Input signal lines L.sub.I1 to L.sub.I8 are connected to input terminals IN1 to IN4 and IN1 to IN4, as shown. Input signals A to D are applied to the input terminals IN1 to IN4, respectively. Inverse input signals A to D, which are in opposite phase to those A to D, are inputted to the input terminals IN1 to IN4, respectively.
A decimal coded input signal `0` is taken out from an output terminal OUT1 which is a connecting point between the group of the transistors N1 to N4 within the block 12 and the group of the transistors P1 to P4 within the block 18. OUT2 is a connection point between the transistor block 14 and the transistor block 20, from which a decimal coded output signal `5` is taken out. OUT3 is a connection point between the transistor block 16 and the transistor block 22, from which a decimal code output signal `9` is taken out.
Reference characters A to D designate input signals applied to the input terminals IN1 to IN4. Characters A to D are input signals applied to the input terminals IN1 to IN4, respectively, which are in opposite phase with the input signals A to D.
In the CMOS decoder with such a construction, the decimal coded output signals `0,` `5,` and `9` are expressed by the following logical expressions
______________________________________ ##STR1## ##STR2## ##STR3## ______________________________________
The conventional decoder including the CMOS logic circuits as shown in FIG. 1 is problematic in the integrated fabrication and the switching speed.
Generally, the mobility .mu. (p) of a hole is slower than that of .mu. (n) of an electron. Therefore, a circuit connection with P channel MOS transistors connected in series, as shown in FIG. 1, is not preferable in the light of the switching speed. Further, in the circuit arrangement shown in FIG. 1, the input lines L.sub.I1 to L.sub.I8 must be formed entering not only an area where the N channel MOS transistors are formed as indicated by 12, 14 and 16, but also an area where the P channel MOS transistors are formed as indicated 18, 20 and 22. The line formation extending to the P channel MOS transistor area superfluously occupies a chip area, resulting in ineffective utilization of the chip area.